Full-Speed Test Design Based on Memory Built-in Self-test

Memory built-in-self-test has become a major method to test embedded memory in design-for-testability.Based on a traditional memory built-in-self-test in a Ethernet chip, proposes a multistage pipeline stage full-speed test instruction, decrease read and write clock cycle in test, shorten test time, reduce test cost.After simulation verification, it proves the pipeline stage instruction can raise built-in-self-test efficiency.