Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System

This paper presents an embedded Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System using TI TMS320C6455 DSP and Virtex5 FPGA, which can achieve 2.5 Gsps five-channel -time-interleaved Parallel Signal Acquisition and 10G RapidIO routing. The sample-timing error algorithm of signal reconstruction based Farrow filter is realized in FPGA, and by configure the high-speed serial port and the routing chip the high-speed communication mechanism can be extended. By analyzing the hardware architecture and resource of embedded platform, the efficient DSP-based compute is described.