The Design and Simulation of a Fault-Tolerant Array Structure in Reconfigurable Circuit

To solve the fault of PE (processing element) on reconfigurable circuit, presents a practical fault-tolerant solutions. By analyzing and deriving the error probability of PE array and hardware cost, the conclusions is obcaired that only one spare PE is needed in each row for dealing with the error in 4×4 PE array, then an effective fault-tolerant program is prooosed and the functional simulation and FPGA verification to the circuit are completed. The result show that this design can make full use of spare PEs and repair the fault, and its integrated frequency is up to 203 MHz when using Design Compiler in SMIC 0.13 μm CMOS process standard cell library.