Research and Design of ECC Acceleration Array for Multi-core

In order to make cipher multi-core processor support ECC cryptographic algorithms, the ECC arithmetic operation characteristics are extracted, and a ECC acceleration array structure for cipher multi-core processor is designed, which can realize dual-domain(prime field and binary field) ECC cryptographic algorithms of arbitrary length within 640 bit. It effectively supports high parallelism degree of ECC algorithms and multi-ECC algorithms parallel accelerating calculation. Implemented in CMOS 0.18 μm technology, circuit maximum clock frequency can reach at 238 MHz. Compared with other literatures, algorithms computing speed is improved and algorithms is supported for a wider range.