A Low Power Implememtation Method on Processor Based on In-Situ AVS Technique

In order to excessively reduce power dissipation of the ARM Cortex M0 processor, we propose a Low power implememtation circiut based on In-Situ AVS Technique. The main process is to estimate the monitoring window(ΔT) and pre-error limit number(n_limit) which determings the voltage adjusting through the path delay of the circuit. Besides, the In-Situ Delay Monitor replaces the flip-flops at the end of critical paths. After detecting the path delay and pre-error using the In-Situ Delay Monitor, the circuit voltage could be adaptively adjusted through the AVS control unit and voltage regulator with the varying of PVTA, which is an efficient scheme to tune the supply voltage of digital circuits according to variations. We have designed a Arm Cortex M0 processor in the SMIC 180 ns process, and applied this method to a critical module(AHB to APB bridge). As a result, We simulated the power dissipation, and find that the circuit applied AVS technique has reduced 28% with the pre-error rate of 8.9E-4 during a observation interval compared to the design former.