3D IC Design for HEVC Motion Estimation Module

As feature sizes continue to shrink, IC design is faced with the challenges of physical limits. 3D IC based on TSV gradually becomes a hot topic. There is scarcely EDA tool to support 3D IC design. In order to overcome this difficulty, 2D commercial EDA tools are combined with custom scripts to form a complete 3D IC design flow. This flow is used to accomplish 3D IC design of HEVC motion estimation module. The 3D circuit partition and physical design of HEVC motion estimation circuit are introduced, including placement, routing, clock tree synthesis and timing verification. The results show that the 3D HEVC motion estimation circuit decreases 75% of footprint area, 14.4% of total wire length, 17.1% of average wire length and 12.3% of power consumption compared to 2D design.