SHAN Tian-long, ZHANG Jia-qi, ZHOU Ji-qin. Modular Design of the UM-BUS Test System[J]. Microelectronics & Computer, 2015, 32(7): 147-151,156. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.034
Citation: SHAN Tian-long, ZHANG Jia-qi, ZHOU Ji-qin. Modular Design of the UM-BUS Test System[J]. Microelectronics & Computer, 2015, 32(7): 147-151,156. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.034

Modular Design of the UM-BUS Test System

  • Dynamically reconfigurable high-speed serial bus UM-BUS can reconfigure itself to achieve fault tolerance with multi-channel concurrent redundancy. UM-BUS test system is responsible for data monitoring and bus statue analyzing through collect and process bus data. The effective bandwidth of UM-BUS can up to 149.5MB/s at 8 lanes. In order to collect the high speed data on 8 lanes bus, the cache and USB3.0 are designed in the test system to store and transmit data. The experiment result indicates that the test system has ability to collect high speed UM-BUS data reliably. The performance of UM-BUS test system lays the foundation of bus statue analyzing and specific monitoring.
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