FPGA Implementation of Parallel Frame Synchronization System Based on CCSDS

An method to perform high speed parallel frame synchronization based on CCSDS standard and FPGA technology is presented for data throughput in space communication.Firstly,logic simulation is made on Modelsim SE-64 10.2.The synthesis and implementation are made according to ISE Design Suite 14.4, and board test is performed in Xilinx Kintex-7 XC7K325T.Its implementation on Xilinx Kintex-7 XC7K325T achieves a data throughput up to 1Gbit/s.The simulation and test results show that with parallel architecture and pipeline architecture,the frame synchronization speed is improved enormously and steadily. The design also takes error margin into account.