ZHENG Xin-jian, TIAN Ze, ZHANG Jun. Design and Implementation of a Low Power Instruction Cache[J]. Microelectronics & Computer, 2015, 32(7): 25-28. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.006
Citation: ZHENG Xin-jian, TIAN Ze, ZHANG Jun. Design and Implementation of a Low Power Instruction Cache[J]. Microelectronics & Computer, 2015, 32(7): 25-28. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.006

Design and Implementation of a Low Power Instruction Cache

  • The main power consumption of instruction cache comes from the access to data memory and tag memory. Access to tag memory need only once per line during sequential execution. The branch prediction and Cache Pre-access can reduce the access to tag memory and data memory significantly. The method can reduce cache power while retaining its performance. A Branch Prediction and Cache Pre-access(BPPA) method is presented in this paper to reduce the cache power consumption. The power simulation result shows it can reduce about 30% power consumption with different applications.
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