Designing a High Performance Network Adapter in Support of Network on Chip Fault Tolerance

A high performance network adapter is proposed to support NoC fault tolerance using dual redundant network interfaces.Using this method data can be transmitted in high throughput across different clock domains. Moreover, several fault-tolerant solutions have been implemented including data validation, link failure detection and network congestion control to improve the reliability of overall system. Experimental results show that the communication performance of the proposal is increased by 63.53% than others using I/O mode with improving system parallel processing capability. The number of successfully delivered packets is enhanced approximately 183% compared with no fault tolerance designing.