Thinking on single-pair ethernet physical layer analog front-end design

Single-Pair Ethernet(SPE) is a new Ethernet technology in recent years. With the rapid development of automobile self-driving and industrial Internet of Things(IoT), SPE is being used on a large scale with its absolute advantages of upper-layer application expansion and bottom-layer cabling. SPE physical layer analog front-end technology is the key basic technology to realize SPE communication. This paper describes the existing standards, architecture and relevant module design technologies related to the physical layer analog front-end of SPE, focusing on the existing implementation technologies of TX and RX key modules and their advantages and disadvantages. TX current-mode structure is easy to achieve high accuracy but low power consumption efficiency, while voltage-mode structure has slightly lower accuracy but higher power consumption efficiency.The design of RX is carried out around Analog-to-Digital Converter(ADC), which determines the performance, power consumption, area and complexity of the whole RX. Segmentation And Reassembly(SAR) ADC is the preferred structure, and the upper limit of application continues to increase. This further identifies the challenges in the design of high-performance, low-power, small-area SPE physical layer analog front-end.