A design of high PSRR low noise LDO circuit based on active filter circuit

In order to reduce the noise in the Low Dropout Regulator(LDO) circuit and the ripple carried by the input voltage on the output voltage accuracy, a circuit design technique based on the idea of active filtering is proposed to optimize LDO noise and Power Supply Rejection Ratio(PSRR), and a multi-stage regulated design is adopted to greatly improve the PSRR of LDO without considering power consumption and dropout voltage. The input voltage is regulated by the pre-LDO circuit, and the subsequent circuit is powered after a secondary power supply is formed, and an additional stage of regulation circuitry is added to the reference of the post-stage LDO to regulate the voltage and reduce loop noise through a low-power RC filter and transimpedance amplifier. In addition, a low-noise feedforward circuit and a fast start-up circuit are added to improve the response speed of the LDO. Based on the 0.18 μm BCD process, under the simulation verification of 5 V input 3.3 V output and 10 mA load current, the overall circuit is measured to reach −110 dB PSRR at 1 kHz, and its noise is only 5.3 μVrms at 10 - 100 kHz. At the same time, by simulating the PSRR and noise of the LDO by changing the load capacitance and load current of the reference, the results meet the design requirements and effectively improve the accuracy of the LDO output voltage.