Design of a 56 Gb/s PAM-4 optical receiver front-end in 45 nm SOI CMOS

In optical receiver design, the parasitic capacitance of the photodiode and the large input resistance will reduce the bandwidth of the receiver, causing serious inter-symbol interference (ISI). Noise is one of the most important metrics of the high-speed transimpedance amplifier (TIA), and the transimpedance value determines the noise performance of the system while also limits the data rate. An optical receiver front-end based on 45 nm Silicon-On-Insulator(SOI) process for 4-level Pulse Amplitude Modulation (PAM-4) working at 56 Gbit/s (28 Gbaud/s) is presented tailored to 100G/400G optical receiver applications. A low-bandwidth TIA and a g_m/g_m amplifier for bandwidth expansion form a two-stage front-end that improves noise performance while effectively expanding bandwidth. The inverter structure is used to increase transconductance and improve linearity in advanced Complementary Metal Oxide Semiconductor(CMOS) technology. The variable gain amplifier (VGA) is designed with a folded Gilbert structure and uses a parallel peaking inductor to expand bandwidth. The dynamic range of the overall circuit is 51.6 dB to 70.6 dB, and the −3 dB bandwidth reaches 20.1 GHz. The input referred noise current density is 17.3 \mathrmpA/Hz^\frac12 . The circuit is implemented in GF 45 nm SOI CMOS, dissipating 65 mW of power from 1.1 V and 1.3 V supply. The layout core area is 600 μm *240 μm.