Design of capacitive digital isolator codec circuit

Aiming at the transmission reliability and current consumption of the capacitive digital isolator at "high speed", a coding and decoding circuit based on the fully differential digital isolator structure is designed based on the TSMC 180 nm BCD(BipolarCMOSDMOS) process.In the transmitter module, the input signal is filtered by Schmitt flip-flop, and the carrier signal is generated by a three-stage current-deficient ring oscillator. The input signal is synchronized with the carrier signal through the D trigger, and then mix with the carrier signal. The mixing signal is differentially output through the driver circuit. A preamplifier is set at the front end of the receiver module to amplify the decayed mixing signal. A bias clamp circuit composed of NPN and PNP triode provides common-mode voltage to the preamplifier. After the preamplifier, a level conversion module is connected. The decoder circuit converts the signal frequency into voltage by RC time constant, and outputs the decoded signal by comparing it with the reference voltage. The simulation results under Process Verification Test(PVT) show that the maximum transmission rate of 25 Mbps can be achieved and the typical transmission delay is 11 ns when the supply voltage is 3.3-5 V. At the transmission rates of 1 Mbps and 25 Mbps, the dynamic power consumption is 2.1 mA and 2.8 mA respectively. The input random code sequences generated by the Linear Feedback Shift Register (LFSR) can accurately implement the codec function at a transmission rate of 10 Mbps. It shows that this design has strong transmission reliability.