A high-efficiency tri-loop architecture digital LDO circuit

A tri-loop structure digital Low DropOut Regulator(LDO) circuit without off-chip capacitors fabricated by 0.18 µm Complementary Metal Oxide Semiconductor(CMOS) process is designed, the main innovation is in the control method, and the corresponding loop adjustment is adopted for different output voltage ranges. Its power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) array is divided into three groups, that is large(L), medium(M) and small(S) according to the size of the MOS tube. The designed control method allows the loop to switch quickly according to the load change, so that the circuit has a fast transient response. Strong load capacity, low output voltage ripple and power consumption, and the highest conversion efficiency is 88.9%. The post-simulation results under the input voltage of 1.8 V show that when the load current suddenly changes between 2 mA and 60 mA, the undershoot voltage of the circuit is 95 mV, the overshoot voltage is 80 mV, and the stabilization time is less than 1.7 μs. The voltage ripple is less than 2.0 mV and the overall quiescent current is about 43 μA. The input voltage range of this digital LDO is 1-1.8 V, and the output voltage range is 0.8-1.6 V. The internal 10 pF capacitor is integrated, and the quality factor FOM is only 0.009 pF.