FPGA decoding of asynchronous BiSS-C protocol

In order to obtain the data transmitted by BiSS-C when the Master(MA) clock of BiSS-C protocol and the Field Programmable Gate Array(FPGA) clock are asynchronous, an implementation method of FPGA decoding BiSS-C protocol under asynchronous clock is proposed. First, the encoder data transmitted by BiSS-C are sampled 16 times in the FPGA, and the BiSS-C data are decoded by the state machine and Cyclic Redundancy Check (CRC) is performed on the data. Secondly, the FPGA software is simulated in ModelSim to verify the function of the state machine and the data interpretation ability of the FPGA software. Finally, the encoder data acquisition system is built to verify the decoding effect of FPGA. The simulation results and experimental results show that the FPGA can correctly decode the data transmitted by the BiSS-C protocol under the asynchronous clock. The decoded encoder angular position error is not greater than 0.1 arcseconds, with low bit error rate and high decoding accuracy.