Embedded microfluidic cooling technology for large-area processing chips

As the integrated circuit process reaches the limit, Dennard's scaling law gradually fails, and the power density of the chip continues to grow. Especially driven by the rapid development of 5G, the Internet of Things and high-performance computing, the single-chip area is increasing rapidly, and the thermal dissipation problem is becoming more serious. The traditional cooling method cannot guarantee the reliability of chip operation. Embedded cooling can avoid the thermal resistance of the packaging material and the multilayer interface, which can also improve the cooling performance and efficiency. Much fruitful research and exploration have been carried out in academia on embedded microfluidic cooling of chips. New channel structure design solutions are constantly proposed, such as parallel long straight channels, manifold channels, jet channels, etc. It is designed to optimize pump power and thermal resistance for efficient cooling at small pressure drops. However, with the increased chip size, achieving efficient cooling in the restricted space will be more difficult. The process difficulty and manufacturing cost limit the large-scale commercial use of embedded liquid cooling. The current cooling scheme demonstrated in the actual IC chip verifies the performance of embedded cooling. Still, these cases have high complexity and poor compatibility, and cooling performance needs to be further improved. In particular, with 3D packaging architecture, it is necessary to propose a channel structure compatible with miniaturization and high-density packaging to achieve inter-layer cooling through electrical-thermal co-design. While optimizing the channel structure design, it is also necessary to simplify the process, reduce costs and improve the process reliability and long-term operational reliability of embedded microfluidic cooling to advance the practical application of embedded microfluidic cooling technology.