Comparator offset calibration circuit for ADC array of computing-in-memory

A dynamic comparator offset calibration circuit for computing-in-memory array is proposed. The digital assisted analog calibration technology is adopted and the calibration voltage is shared globally according to the characteristics of array application. The calibration process is divided into the coarse and fine calibration, helping to improve the calibration speed and accuracy. Coarse calibration uses a 6-bit counter and Digital to Analog Converter(DAC) to generate a step-type calibration voltage. The calibration voltage is connected to the corresponding current compensation circuit according to the initial offset voltage polarity. The value of the offset voltage is rapidly reduced and its polarity is changed by a large calibration step. Fine calibration uses a time-delay adjustable circuit based on transistor gate voltage regulation. The fine calibration voltage is generated by a 10-bit counter and DAC to achieve fine adjustment of the offset voltage value. The comparator calibration logic circuit is designed based on simple gate circuit and flip-flop. Under the control of global calibration signal, the local calibration switch and calibration phase can be converted. With the global sharing of calibration voltage, the comparator only needs to add the calibration logic circuit, current compensation circuit and adjustable delay circuit. As a result, the area caused by the calibration circuit is effectively reduced. The simulation results based on a 55 nm Complementary Metal Oxide Semiconductor(CMOS) process shows that, under the 50 MHz input clock, the offset calibration range is ±20 mV. After calibration, the offset voltage is 0.96 mV (3.3σ) and presents a more uniform distribution. The layout area containing calibration circuits is 696.28 μm².