Design of a low jitter current mode self-biased phase-locked loop

Based on 28 nm CMOS process, a new current mode self-biased phase-locked loop is designed. The circuit design and functions of charge pump, voltage to current (V-I) module, current mode Digital to Analog Converter (DAC) and Current Controlled Oscillator (CCO) are analyzed in detail. The technology of Replica Feedback Bias is adopted to realize bandwidth adaptation. The programmable IDAC module is used to reduce the impact of the input range on the system stability and eliminate the impact of the allocation range on the loop stability. The front divider is used to further expand the input frequency range and realize the design of a wide input and output frequency range and a low jitter current mode phase-locked loop. The overall chip area is 0.074 62 mm², the dual power supply is used to supply 1.8 V/0.9 V, the maximum power consumption is 10 mW, and the output frequency is 1 GHz~3.2 GHz. The simulation test results show that when the input reference frequency is 50 MHz, the phase noise at the center frequency 1 MHz offset of 2.1 GHz is −98.18 dBc/Hz, and the rms jitter is 1.914 ps.