A real-time image mosaic and fusion circuit design based on FPGA

Image mosaic is broadly applied in many fields such as panorama, whose key technologies include image registration and image fusion. To obtain low-cost and real-time processing, circuit design for image mosaic should be carried out, while most researches focus on image registration and ignore image fusion algorithms, not to say specific circuit design. Normally, image registration algorithm circuit and peripheral controller consume most of chip resources for their complexity. Therefore, the performance and resource utilization of image fusion circuit are two critical factors affecting the performance of the whole image mosaic system. In order to achieve real-time fusion after image registration with high efficiency and low resource utilization, an image fusion algorithm circuit based on greedy algorithm to search for seam is proposed, forming a complete prototype verification test system from image data source to display. The synthesis result based on the Cyclone IV Field Programmable Gate Array(FPGA) device and theoretical analysis show that the proposed circuit can complete fusion of two 486×643 images at the clock frequency of 100 MHz while maintaining low resource utilization and display effect, which takes 6.5795 ms, about 144 FPS, meeting the real-time requirements, and the processing rate is better than the three comparison objects through theoretical conversion.