High performance FPGA implementation for SM3 algorithm

The high-performance implementation of the existing SM3 algorithm is mainly to adopt a multi-stage pipeline structure and different critical path optimization strategies, and improve the throughput achieved by the SM3 algorithm. However, multi-level pipelines require a lot of hardware resources. This paper first fully exploits the parallelism of the SM3 algorithm in the FPGA platform, reduces the logic depth of the algorithm critical path by adding a small number of registers, and uses only 1211 LUT logic resources to achieve the throughput of a single core of 2.55 Gbit/s by executing in parallel with the message extension and compression functions, which is 5.40 times higher than the throughput per logical resource of the existing program, with a smaller area, lower power consumption and higher performance. Finally, based on this structure, the SM3 algorithm hardware with 32 cores was designed, which could achieve higher throughput than the existing 64-level pipeline structure, and the hardware overhead was lower, and the throughput per logical resource was increased by 2.27 times.