A high speed SLVS driver circuit for MIPI D-PHY applications

This paper introduces a high-speed SLVS driver circuit for MIPI D-PHY, which is manufactured by SMIC 14nm FinFET process. The problem of the delay of pull-down network in traditional level lifting structure is analyzed. By using neutralization capacitor to reduce feedback noise, and adding adjustment branch in cross coupling structure to balance pull-up network and pull-down network, the output node can be charged and discharged more quickly. To solve the problem of signal overshoot caused by parasitic capacitance during the conversion of the drive circuit, the coupling capacitance is added to weaken the current flowing through the transistor during the conversion, reduce the output signal overshoot, and reduce the common mode disturbance caused by the switch during the conversion. In the traditional drive scheme, the source leakage voltage of the switch and tail current tube is too low, which leads to excessive area overhead. The area of the transistor is saved by paralleling the switch control path with the common mode feedback adjustment path. In order to compensate the attenuation of the channel to the high frequency component of the signal, the high frequency component of the signal is increased by detecting the signal jump and generating a pulse signal to drive the pre emphasis circuit, so as to improve the eye map quality and achieve higher frequency data transmission. The test results show that under the 1.8 V power supply voltage, the output common mode level is 200 mV, the voltage swing is 200 mV, the working speed is up to 4 Gbps, the total power consumption is about 4.25 mW, and the energy efficiency is 1.0625 mW/Gb/s. The horizontal opening of the output eye map after structure optimization at 3.6 Gbps and 4 Gbps speeds increased by 0.08 UI and 0.07 UI respectively.