Thermal stress analysis of all-copper interconnection in 3D IC

Compared with the two-dimensional packaging, 3D IC (3D Integrated Circuit) technology has the characteristics of shorter interconnection length, better heterogeneous integration, lower power consumption and smaller package size. All-copper interconnection structures are used in 3D IC instead of solder balls because of the excellent electrical conductivity, electromigration resistance, and mechanical properties of copper matrix. In this paper, the thermal reliability of the 3D IC model with all-copper interconnection and micropin-fin structure is studied by numerical simulation, and the influence of the height of all-copper interconnection on the thermal stress inside the model is analyzed. The results show that the maximum thermal stress of the all-copper interconnection part is related to the spatial position of the copper pillar. The farther away from the center of the model, the greater the deformation in the copper pillar. At the same time, the internal stress distribution and deformation of the dangerous copper pillar show that due to the different nature of the load on the upper and lower end faces of the copper pillar, the Mises stress of the copper pillar under the action of thermal load is roughly symmetrically distributed left and right and up and down. This phenomenon can lead to a potential failure mode of the copper pillar that is fractured or damaged under axial compression and shear combined. In addition, the thermal stress gradually decreases with the increase of the copper pillar height, and the maximum thermal stress tends to be stable when the copper pillar height is 300 μm, which can provide a reference for the reliability design of all-copper interconnects.