A highly energy efficient local clock network design based on improved K-means algorithm

Aiming at the problems of wide load distribution, long clock insertion delay and difficult to control skew faced by the design of block level clock network in advanced processor, this paper proposes an energy-efficient local clock network design method. A clock driving position optimization method based on K-means algorithm considering load called TKDLO algorithm is proposed and implemented compiled with current EDA flow. Test results show that the average improvement for module level clock insertion delay is about 15% along with 30% skew reduction. Notably, taking the clock network design of memory access execution block as an example, compared with the implementation of traditional CTS, the local clock design method proposed in this paper achieves more than 50% optimization in clock insertion delay and skew. The equivalent frequency of the whole design is improved by 14%, the average power consumption is optimized by 28%, and the energy efficiency of the block is improved by 81.2%. Compared with the fishbone clock structure based on sequential clustering, the local clock design method proposed in this paper can increase the frequency of the module by 7.6% and optimize the energy efficiency by 14.2% at the cost of 15.2% clock insertion delay and 5% power.