A fast transient response LDO circuit design without off-chip capacitance

In this paper, a low dropout linear regulator (LDO) with fast transient response and no off-chip capacitance is designed based on SMIC 65 nm process. An error amplifier with a high gain transconductance structure (OTA) is used to increase the amplifier transconductance using a local common-mode feedback structure (CFRFC), which greatly improves the dc gain and conversion rate of the amplifier. A transient detection circuit consisting of a capacitor-coupled current mirror is introduced to improve the loop transient response speed, stabilize the loop and reduce the LDO up/down voltage. A super source follower is used in the buffer stage to increase the dynamic current at a certain static power consumption, pushing the secondary point to a higher frequency and improving the phase margin of the circuit. Simulation results show that the circuit outputs 1 V at an input voltage of 2~3 V with a maximum load current of 100 mA; the maximum overshoot and undershoot voltages of the LDO output are 23 mV and 27 mV when the load current is in the range of 0~100 mA, and it has a high supply rejection ratio at low frequencies.