Verification design of PCIe bridge chip based on UVM

RapidIO protocol is a packet-switching interconnection protocol designed for high-performance embedded systems. PCIe(Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard that provides point-to-point dual-channel high-bandwidth transmission. The existing domestic CPUs do not support the RapidIO interface, and can only be connected to the switching network through PCIe to RapidIO bridge chips. The development of domestic PCIe bridge chips is of great significance to the promotion of domestic CPUs. This paper optimizes on the basis of the traditional UVM(Universal Verification Methodology) architecture, adopts the method of real-time comparison based on single descriptor. In scoreboard, changed the comparison data from the data link layer of PCIe VIP to make the BDMA engine memory occupancy rate is reduced by 30%, and the total simulation time of the verification platform is shortened by 25%; the method of automatic integration of the register model is adopted to conduct cross access to the front door and the back door of the register, and the properties and initial values of the registers can be quickly verified. The total verification time of the register is reduced to 20% of the original, and the correct rate can reach more than 95%. This method is especially suitable for the verification of registers with different attributes of each field of the same register; The code coverage rate is collected, reaching 100% coverage, that reached the expected requirements, the platform can be used for verification of digital chips.