SONG W N,XU D J,CHEN L. Overview of DSP architecture development[J]. Microelectronics & Computer,2023,40(4):1-7. doi: 10.19304/J.ISSN1000-7180.2022.0456
Citation: SONG W N,XU D J,CHEN L. Overview of DSP architecture development[J]. Microelectronics & Computer,2023,40(4):1-7. doi: 10.19304/J.ISSN1000-7180.2022.0456

Overview of DSP architecture development

  • Digital signal processor (DSP) is a special microprocessor for digital signal processing, which has important application value in communication, automation, radar, aerospace and other fields. This paper systematically expounds the development process and current situation of DSP architecture, and introduces the DSP products and performance of the main manufacturers; Moreover, the main structure characteristics of DSP chip are summarized; This paper also analyzes the main techniques for improving data level and instruction level parallelism in the existing DSP architecture design, including Harvard architecture, hardware multiplier, SIMD, VLIW and superscalar. Combined with the application requirements of DSP in the new era, this paper proposes three development directions of DSP architecture research: (1) Increasing the parallelism of data and instructions could move DSP toward ultra-high performance. Improving the vector and scalar parallel ability, supporting tensor calculation, integrating special control channels and functional units for neural network operators can promote the AI computing processing ability. (2) Starting from the instruction system, combining a variable-length instruction set with superscalar technology to realize instruction parallelism, and at the same time, the computational flow control instruction that can adapt to the expansion of neural network algorithm is combined to improve the mapping ability of AI algorithm, and meanwhile reducing the code density, the storage pressure and the fetch bandwidth, minimizing the cost, and improving the edge intelligent real-time processing application ability; (3) The compatible distributed storage structure of compression and concurrent access for sparse neural networks can enhance the edge intelligent on-chip deployment capability and the network layer multi-channel parallel computing capability.
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