ADPLL circuit design with fast lock time

Fast locking is one of the key metrics of an all-digital phase-locked loop (ADPLL). Ideally, the lockout time should be as short as possible. Traditionally structured ADPLL (TS-ADPLL) typically use adaptive bandwidth techniques or numerically controlled oscillator (DCO) tuning words and preset techniques to reduce lock time. However, both adaptive bandwidth technology and preset technology require additional modules, which will add additional power consumption. In order to improve the locking speed of the all-digital phase-locked loop, an all-digital phase-locked loop (ADPLL) circuit based on high-resolution time-to-digital converter (TDC) for fast locking is proposed in this paper. Among them, the TDC circuit adopts a structure combining a double-stage flip-flop and a tapped delay chain, which not only improves the signal tolerance of the circuit, but also improves the resolution of the quantization error signal and the locking speed of the circuit. At the same time, the identification of the lead or lag of the reference signal is completed through the dual SR latches, which can better detect the phase relationship between the reference signal and the output signal, which is beneficial to the system's phase adjustment of the output signal and signal locking. The verification simulation is carried out using XILINX Artix-7 FPGA device. The simulation results show that the locking time of the ADPLL can reach 3.9 μs, and its locking range is 4.7 MHz~35.7 MHz. The ADPLL circuit has the characteristics of fast locking speed and large locking range.