Modeling and analysis of low-power supply networks for digital integrated circuits

In low-power design, the multi-power multi-voltage technology usually uses the Power State Table (PST) to define the power state combination of each voltage domain. When the number of PSTs is large, EDA (Electronic Design Automation) is slow in merging PSTs. Aiming at this problem, this paper proposes a modeling method of low-power power supply network of digital integrated circuits based on the idea of divide and conquer. It uses the divide and conquer algorithm to divide the power supply network into sub-modules, and uses binary search and hash algorithm to accelerate the modeling process. Optimized to increase modeling speed by an average of about one-third over linear search. All PSTs in the model are then quickly merged using a dual mapping algorithm and parallel computation. Finally, the UPF test set is designed to verify the correctness of the model and test the analysis speed of the model. In the test of 500 UPF (Unified Power Format) files, the correct rate of analysis results is 100%. In 10 performance test sets, it is found that the speed is about 115 times faster than that of the international mainstream LP tools.