Fault test design of STT-MRAM memories

Spin transfer torque magnetic random access memory (STT-MRAM) stands out among the new memory because of its nonvolatile, fast read and write speed, long data retention time, and full compatibility with CMOS (comprehensive metal oxide semiconductor) process. With the rapid increase of its industrialization investment and the expansion of its application scale, it is necessary to test the quality and reliability of STT-MRAM memory products. At present, when the most commonly used March test algorithm verifies the performance of STT-MRAM, there is a problem that the complexity and fault coverage do not match. In view of this, starting from the formation and classification of manufacturing defects in STT-MRAM, this paper adopts the mode of March detection to sensitize some expression of pinhole faults, and based on such fault types, proposes a March CM test algorithm with high fault coverage. According to this algorithm, the corresponding build in self testing (BIST) circuit is designed.Simulation and board level test of STT-MRAM show that the design meets the test requirements of high complexity and high coverage.