A SIP schematic rule checking error back-marking tool integrated in OrCAD Capture CIS

System-in-Packet (SiP) technology integrates multiple subsystems in one package, which has the advantages of flexible assembly method and short development cycle, and has broad development prospects in the process of miniaturization of electronic equipment. In the SiP design process, whether the schematic design is correct often determines the success or failure of the overall design. However, connectivity errors in schematic designs often require engineers to spend a lot of time looking for comparisons to pinpoint the location of the error. In order to improve the efficiency of schematic connectivity error checking, this paper proposes a connectivity rule checking error back-marking tool applied to the SiP system-in-package schematic design stage. The tool is integrated into the OrCAD Capture CIS tool in the form of a plug-in, which can cooperate with the existing schematic rule checking tool, so that users can obtain and analyze the valid error information generated by the rule checking tool through the graphical interface, and the error information is clear and intuitive. By performing an error back-labeling test on a test system consisting of 26 pages of schematics, the tool can back-label the connectivity error information in the schematic to the corresponding location on the schematic within seconds, allowing designers to quickly locate the wrong location, which effectively improves the efficiency of the connectivity check in the schematic design stage.