Design of PLB to AXI bus bridge for multi-core system

For the need of convention between PLB and AXI protocol in multi-core system, the bus protocol and memory access behavior of PowerPC processor are studied firstly. The high-efficiency conversion strategies such as pipeline control and read-write superposition are further studied. Finally, the cache coherency maintenance strategy for multi-core system applications is studied. According to the independent characteristics of command signals, read data signals and write data signals, a multi-channel pipeline structure is designed. It realizes the pipelining parallelism of commands and data, and also the interleaving parallelism of read transactions and write transactions. On the basis of pipeline structure, a 2-stage accelerated conversion technology with pipeline-parallel and variable length descriptor is proposed. By importing more continuous bus transactions into the pipeline structure, higher bus conversion efficiency is realized. Refer to the structure and maintenance strategy of cache entries, a cache coherence technology based on dynamic hit prediction is proposed to speed up the process of read commands. Finally, a PLB to AXI bus bridge with full protocol coverage and low conversion delay is realized. The bus bridge is applied to a heterogeneous multi-core architecture chip based on dual-core PowerPC processor, which solves the problem of efficient and reliable conversion from PLB to AXI bus in SoC system. The above design was successfully produced in 65 nm process.