A configuration circuit design for Flash-based FPGA

In order to provide a stable erasing, programming and reading operating voltage for flash switch unit in flash-based FPGA, a configuration circuit for flash-based FPGA was designed based on 0.11 μm 2P8M flash process. According to the operating conditions of flash cell and the characteristics of flash-based FPGA, the configuration circuit is designed with hierarchical word line circuit, bit line circuit with check function, low ripple charge pump circuit, multi-level level conversion circuit, flexible substrate voltage circuit and configuration control circuit, which is the basis of the implementation of the configuration algorithm flow. It provides high precision and stable operating voltage for flash cell in the process of flash-based FPGA configuration, ensures the consistency of threshold voltage distribution of flash cell after erasure and programming, and gives full play to the performance of flash-based FPGA. The simulation results show that the driving capacity of the word line is 1.2 mA, the output voltage is -10.5 V, the error is less than ±0.1 V, and the establishment time is 11.2 μS. The bit line drive capacity is 1.2 mA, the output voltage is 8.8 V, the error is less than ±0.1 V, and the establishment time is 7.5 μS. In programming, the driving capacity of the word line is 1.2 mA, the output voltage is 9.8V, the error is less than ±0.1 V, and the establishment time is 2.1 μS. The bit line drive capacity is 4.4 mA, the output voltage is -8.0 V, the error is less than ±0.1 V, and the establishment time is 2.3 μS. The design meets the operating conditions of Flash cell, and finally realizes the configuration of 3.5 million flash-based FPGA with 26 836 992 bits (2 912 BL * 9 216 WL) bit streams.