Fault-tolerant structure of neural network based on Bayesian optimization

When neural networks are deployed to edge devices in complex environments, various types of failures may occur due to the influence of complex real environments. Therefore, the robustness and potential fault-tolerant characteristics of neural network model are widely concerned. At present, there is a design strategy of fault-tolerant neural network that explicitly increases the computational redundancy, and the reliability is improved by adding the computational layer redundancy structure in the whole convolution. However, this design strategy to achieve high fault tolerance ignores the introduction of a large number of model parameters and computation. Although it can improve the reliability of the network model to a certain extent, this model is not suitable for deployment on embedded devices with limited storage and computation resources. In order to solve this problem, we propose to use Bayesian optimization algorithm to obtain the best computational redundancy structure applied to neural networks to realize reliable neural networks. At the same time, we made a few changes to the accelerator system hardware to find out the key modules that determine the stability of the embedded deployment acceleration system. Compared with the design of full computational redundancy structure, this method can reduce the accuracy of Top5 model by no more than 2.6% and the average computational load by 37.7% with 1e-4 as the uniform error rate.