Design of hardware accelerator based on MobileNet-SSD for object detection algorithm

With the rapid development of Artificial Intelligence, modern convolutional neural network has achieved great success in image recognition and classification. However, the complex neural network model continues to develop to a deeper network structure, which can not maintain high performance and high accuracy when deployed on mobile devices with limited area and power consumption. To solve this problem, a design of MobileNet-SSD object detection hardware accelerator based on software-hardware cooperation approach is proposed for FPGA platform. Firstly, pruning and quantization algorithms are used to compress the original MobileNet-SSD model. Pruning is a convolution kernel pruning algorithm proposed for the problem of point-wise convolution layer parameter redundancy, and quantization is to uniformly convert the floating-point numbers in the trained network model into fixed-point numbers to participate in convolution calculation. Then, a configurable convolution computing acceleration array is designed to realize multi-granularity parallelism of different scale network layers through tiling strategy. On this basis, a linebuffer optimization mechanism for input buffer is further designed, which combines Direct Memory Access (DMA) and data stream interface to transfer data to solve the bottleneck of transmission delay. Experiments show that the performance and power consumption of the proposed object detection system are 79× and 1.9× higher than that of CPU and GPU, respectively. Compared with the object detection system proposed in the previous work, it has higher accuracy and better performance.