Design of instruction control system for neural network accelerator

Deep neural networks are increasingly used in the field of intelligent processing of image and speech, however their multiple operator and parameter types, large computation and storage intensive characteristics restrict the application in embedded scenarios such as aerospace and mobile intelligent terminals. To address this problem, the concept of decoupling input data streams for efficient flowing parallel processing is proposed, and an instruction control system for a neural network accelerator is designed. After the input data of different operators are cyclically chunked, and corresponding to the instruction group configuration, multiple state machines collaborate to complete the three-stage distribution control of instruction information, realising four stages of parallel flow of instruction parsing, data input, computation and data output, fully utilising the data reuse possibilities within the chunks, so as to reduce the access bandwidth and flow cycle idle rate. Deployed on the ZCU102 development board, the test shows support for a variety of common neural network layer types and a wide range of parameter configurations. At a frequency of 200M, with a peak arithmetic power of 800 Gops and running the VGG16 network model, an actual test run of 489.4Gops and power consumption of 4.42W resulted in an energy efficiency ratio of 113.3GOPs/W, superior to similar neural network accelerators and CPUs and GPUs. Experimental results show that the method of decomposing data streams and using instruction scheduling to achieve efficient parallelism solves the two major challenges of generality and energy efficiency, the instruction control system based on this method, can provide a solution for the embedded platform application of neural network accelerators.