A method to verification architecture for command timing control of DDR-memory controller

Phase Change Memory (PCM) as a novel memory, has the characteristics of high transmission rate and non-volatility. It can meet the application requirements of both internal and external memory. The memory controller circuit needs to be designed according to its characteristics in the application process. In this paper, a universal verification method (UVM) based verification method for PCM controller using DDR transport protocol is proposed to meet the timing control requirements in the verification process. The method transfers the command timing control function from the sequence module in the UVM to the driver module, simplifies the timing controlling structure by establishing a command queue and time board to optimize this timing control process. To solve the problem of data blocking caused by time gap between PCM's read and write latency, the semaphore in System Verilog is also applied to parallelize the command and data, which brings a simpler code structure to implement the functionality of avoiding data latency blocking commands. The results show that as the number of test cases in the UVM increases, the boost in simulation efficiency of this method will be improved. When the test case increases from 2, 000 to 100, 000, the boost in simulation efficiency increases from 20% to 127%. The parallel control of interpolating write command during read latency is also implemented. The method proposed in this paper optimizes the verification structure of original control circuit, while can also be used as a reference to various DDR memory controllers' verification environments.