A 4-channel extended counting ADC for CMOS image sensor readout

A 15-bit 4-channel extended counting (EC) ADC with correlated multiple sampling (CMS) is designed for low-noise column readout in scientific CMOS image sensors (CISs). The 4-channel EC ADC structure is composed of 4 Incremental ΔΣ ADCs (IADCs) working in parallel and a cyclic ADC to increase the readout speed. The ADC is designed and implemented in a 0.11 μm CMOS process. The readout speed of the 4-channel EC ADC is 133KSPS at 5MHz clock frequency. Simulation results show that the maximum INL and DNL of the ADC with 128 times multiple sampling are -3.32 and -2.58 LSBs, and the CMS brings forth a 9.22 dB improvement in SNR. The power consumption is 650 μW per channel at 3.3 V supply voltage.