Research progress on single event upset test and hardened design of DDR memory

This paper summarizes the research history and current situation of DDR memory single event upset experiments and hardened design at home and abroad, and forecasts its future trend. Researchers at home and abroad have carried out many experiments related to single event upset of DDR memory, and made statistical comparisons of the cross-section and upset threshold of each generation of DDR memory. Through the analysis and summary of the experimental process and results, the relationship between the process, storage capacity, radiation dose and the single event upset cross-section is studied. It was found that with the shrinking of the DDR memory process scale and the increase of the storage capacity, its sensitivity to single event upset also gradually increased. The existing anti-single event upset hardening of DDR memory is mainly divided into process hardening and design hardening, including SOI(silicon-on-insulator), layout hardening, circuit redundancy and error correction code, etc.. The mechanisms of various hardended methods were briefly explained, and the advantages and disadvantages of them were analyzed, and it focused on the hardened design of more universal error correction and detection algorithms, including on-die error correction codes and EDAC (Error Detection and Correction) IP cores. Compared with the detection capability, time delay, area overhead and power consumption of typical error correction codes, it is found that the SEC-DED (Single Error Correction-Double Error Detection) Hamming check code can be used to correct single bit upset, and the orthogonal Latin square code has significant advantages in correcting multiple bit upsets. It provides an idea for the subsequent proposal of a new DDR memory anti-single event upset hardened design.