A novel high-security chip integration technique based on silicon interposer structure

A novel silicon interposer based high-security and high-density chip integration technique was presented in this paper. In the integration schematic, the chips were embedded in the trench in the silicon interposer, which was wet-etched. A high-density three-dimensional metal shielding network, which formed a Faraday cage, was design in the trench structure to protect the chip from all directions. The trench structure was prepared by wet etching method, which has the advantages of simple manufacturing process and low cost, and also makes the metal shielding protection network design more flexible. Three chips were employed to implement the schematic and the detailed processes including wet etching and photolithography were elaborated. The experimental results showed that the technique can achieve physical invasive attack detections with the minimum detection resolution up to 60 microns. Besides, the metal shielding network could significantly reduce the electromagnetic radiation intensity of the chips and enhance the ability to resist electromagnetic side channel attacks.