Analog front-end circuit design for receiver system of 40 Gb/s SerDes

In the high-speed interface circuit, the channel has a great attenuation to the high-frequency components of the transmitted signal, causing the received signal to produce Inter Symbol Interference (ISI), so the receiver needs to use equalization techniques to eliminate interference.For different attenuation channels, not only the attenuation amplitude at the Nyquist frequency is different, but the attenuation amplitude-frequency curve before the Nyquist frequency is also different. Increasing the adjustment range of the equalization can make the compensation more compatible with the channel attenuation.This paper designs a receiver analog front end (AFE) for 4-level Pulse Amplitude Modulation (PAM4) and working at 40 Gbps. The front end consists of a continuous time linear equalizer (Continuous Time Linear Equalizer, CTLE), a variable gain amplifier (Variable Gain Amplifier, VGA) and a buffer (Buffer). CTLE uses degenerate resistance capacitance and inductance peaking technology, the gain at 10 GHz is adjustable in 16 levels from 6.01 dB to 12.46 dB; VGA uses current parallel to control the equivalent transconductance, and the low-frequency gain is -4.53 dB to 5.75 There are 16 levels adjustable in the dB range, and the -3dB bandwidth is 17.6 GHz; Buffer uses spread spectrum technology similar to CTLE, and the -3 dB bandwidth reaches 25 GHz. The equalization range of the overall circuit at 10 GHz is 5.98 dB to 11.85 dB. AFE uses 65nm CMOS process, power supply voltage is 1 V, power consumption is 15.943 mW, layout core area is 300 μm*900 μm.