In-memory computing of STT-MRAM based on 2T1MTJ cell structure

The traditional Von Neumann computing architecture is difficult to balance low latency and low power consumption when processing data-intensive applications. By innovating the data processing architecture and effectively improving the communication efficiency between the processor and the memory, In-memory computing technology is expected to overcome this "memory wall"problem.A general-purpose STT-MRAM based on the 2T1MTJ cell structure in-memory calculation schemeis proposed, which realizes the in-memory logic operation and MRAM memory function by accessing transistors. To evaluate the proposed scheme's performance, a CMOS/MTJ hybrid simulation was performed, which combines SMIC 55nm process with MTJ compact model, and the performance was compared with similar schemes based on 1T1MTJ and 2T2MTJ cell structures. The results show that due to the use of a single logic operation reference cell with the same MTJ as the memory cell, the accuracy of the AND/OR bit logic operation and the cell write accuracy of the 2T1MTJ scheme are better than 1T1MTJ scheme in different MTJ process deviations, TMR, temperature and VDD. Compared with the 2T2MTJ solution, the writing accuracy rate of the proposed solution is 37.1% higher, and the cell area is halved. In addition, an improved 2T1MTJ cell structure using dual-threshold transistors is proposed. Its read and write performance is better than the 2T1MTJ scheme which uses the same access transistor, and the accuracy of cell writing is improved by 9.4%.