PENG Jingtong, ZHU Yongxin, WANG Hui, KONG Xiangcong, ZHANG Qinrun, GUO Zhentang. GRU network for flight-data anomaly detection based on FPGA[J]. Microelectronics & Computer, 2021, 38(11): 67-73. DOI: 10.19304/J.ISSN1000-7180.2021.0103
Citation: PENG Jingtong, ZHU Yongxin, WANG Hui, KONG Xiangcong, ZHANG Qinrun, GUO Zhentang. GRU network for flight-data anomaly detection based on FPGA[J]. Microelectronics & Computer, 2021, 38(11): 67-73. DOI: 10.19304/J.ISSN1000-7180.2021.0103

GRU network for flight-data anomaly detection based on FPGA

  • The anomaly detection of flight data on commercial large aircraft has difficulties in high real-time requirement and massive testing points. The use of traditional time series processing software has disadvantages such as long processing time. This paper proposes a Gated Recurrent Unit(GRU) anomaly detection neural network based on FPGA, which is used for time series analysis of flight vibration data sources for anomaly detection. In order to meet the real-time processing requirements of high frequency sampling data, the implementation of GRU is optimized in many aspects of parallel acceleration. The first is to propose a structured parallel optimization method. The weight parameters are stored in the FPGA on-chip memory and the array is cut in dimensions, so that the weight parameters can be read in parallel in the column dimension, and the parallel calculation optimization of the matrix-vector multiplication is implemented to achieve the efficient calculation efficiency of the GRU network.The first is to propose a structured parallel optimization method. The weight parameters are stored in the FPGA on-chip memory and the array is partition in dimension, so that the weight parameters can be read in parallel in the column dimension, and the parallel calculation optimization of the matrix vector multiplication is implemented to achieve the efficient calculation efficiency of the GRU network. The second is to optimize the calculation method of the GRU network activation function. The use of BRAMs as Lookup-table greatly reduces the delay of activation function operations and the consumption of computing resources in a pipeline way.The third is to adjust the data path of the GRU network. By optimizing the calculation sequence, , the dependence of the two sets of matrix vector multiplication is eliminated, and the critical delay is reduced by 40%. The experimental results show that a hardware accelerator of high energy efficiency ratio is achieved with 10.33GFLOPS throughput and 2.532w power consumption.
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