Design of RISC-V dedicated instructions for GNSS channel decoding

With the increase of global navigation satellite system(GNSS) signals, more and more channel decoding algorithms need to be processed by navigation receivers. Although the traditional method using a coprocessor can improve the efficiency of channel decoding, it consumes a lot of hardware resources. Using software to implement channel decoding can use instruction sets such as DSP and SIMD for acceleration, but these instruction sets are not only extended for channel decoding, and most of the instructions are rarely used in channel decoding algorithms. In this way, the channel decoding efficiency is low. Based on the RISC-V instruction set, seven dedicated instructions are extended for GNSS channel decoding. These dedicated instructions enrich the bit manipulations of RISC-V. Compared with the same channel decoding program, the optimized algorithm code amount is reduced. The BCH and deinterleave algorithm code amount reduced by 50%. The gem5 simulator and self-designed RISC-V processor Nightcore verification results show that the number of cycles of the optimized algorithm is reduced. Among them, the number of operating cycles of the deinterleave algorithm is reduced by 92%.