LIU J,LI J M. Optimization of on-chip clock description based on merged clockdomains[J]. Microelectronics & Computer,2024,41(7):104-109. doi: 10.19304/J.ISSN1000-7180.2023.0425
Citation: LIU J,LI J M. Optimization of on-chip clock description based on merged clockdomains[J]. Microelectronics & Computer,2024,41(7):104-109. doi: 10.19304/J.ISSN1000-7180.2023.0425

Optimization of on-chip clock description based on merged clockdomains

  • There are two ways to describe the behavior of On Chip Clock (OCC) for testability design in multiple clock domains: Clock Control Definition (CCD) and Named Capture Procedure (NCP). However, these two methods have disadvantages: CCD cannot define complex clock schemes and capture schemes, and NCP requires a large number of test vectors and a long running time. In view of this, a combined clock domain NCP method is proposed. The merged clock domain NCP improves the controllability of the clock, capture scheme and flow, and makes up for the lack of CCD control. The experimental data show that the combined clock domain NCP saves about 28% of test vectors and 22% of running time for Stuck At Fault (SAF) and about 18% of test vectors and 13% of running time for Transition Delay Fault (TDF) without affecting the coverage rate. The efficiency of test vectors is improved to make up for the shortage of NCP.
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