谢晋,李景虎,吴思妮,等.高稳定性快速响应的无片外电容LDO设计[J]. 微电子学与计算机,2024,41(7):119-126. doi: 10.19304/J.ISSN1000-7180.2023.0522
引用本文: 谢晋,李景虎,吴思妮,等.高稳定性快速响应的无片外电容LDO设计[J]. 微电子学与计算机,2024,41(7):119-126. doi: 10.19304/J.ISSN1000-7180.2023.0522
XIE J,LI J H,WU S N,et al. Design of high stability and fast response LDO without external capacitors[J]. Microelectronics & Computer,2024,41(7):119-126. doi: 10.19304/J.ISSN1000-7180.2023.0522
Citation: XIE J,LI J H,WU S N,et al. Design of high stability and fast response LDO without external capacitors[J]. Microelectronics & Computer,2024,41(7):119-126. doi: 10.19304/J.ISSN1000-7180.2023.0522

高稳定性快速响应的无片外电容LDO设计

Design of high stability and fast response LDO without external capacitors

  • 摘要: 针对光通信集成电路及片上系统的电源与电路之间相互干扰的问题,基于TSMC 65 nm CMOS工艺,设计了一种高稳定性、快速响应的无片外电容低压差线性稳压器(Capacitor-Less Low Dropout Regulator, CL-LDO)。LDO电路包括带隙基准模块、推挽误差放大器、电源抑制比(Power Supply Rejection, PSR)增强电路和尖峰抑制电路。推挽误差放大器为共栅极输入,有效降低了输出阻抗。放大器交叉耦合输入的方式显著提升了功率管摆率,内部添加拓补结构解决了环路增益过低及对称性差的问题,采用密勒补偿实现了0 ~ 100 pF全负载电容条件下系统稳定。主环路结合尖峰抑制电路改善瞬态性能,PSR增强电路产生可修调的负电容消除了功率管栅端产生的电源纹波,有效提升了LDO中频段电源抑制比。仿真结果表明,负载电流在0 ~ 100 mA内,该LDO的上冲电压和下冲电压分别为58 mV和89 mV,最小恢复时间为1.2 μs,全负载范围内最差的相位裕度为64°,空载状态下的电源抑制比为99.2 dB@10 kHz,在不同工艺角下最差的负载调整率和线性调整率分别为0.016 mV/mA和5.1 mV/V。

     

    Abstract: To solve the issue of mutual interference between power source and circuit in optical communication integrated circuit and system-on-chip for optical communication, a high stability and fast response capacitor-less low dropout regulator (CL-LDO) is designed based on TSMC 65 nm CMOS technology. The LDO circuit comprises a bandgap reference module, a push-pull error amplifier, a power supply rejection(PSR) enhancement circuit, and a spike rejection circuit. The push-pull error amplifier with common gate input effectively reduces the output impedance. The amplifier's cross-coupling input significantly improves the slew rate in pass transistor. The internal topology structure solves the problem of low loop gain and poor symmetry. The Miller compensation is adopted to achieve system stability under full load capacitance of 0-100 pF. The main loop combined with spike rejection circuit improves transient performance. The power supply rejection enhancement circuit generates an adjustable negative capacitance to eliminate power supply ripple at the gate of the pass transistor, thus effectively improving the power supply rejection ratio in the intermediate frequency band of the LDO. Simulation results show that within a load current range of 0-100 mA, the LDO's overshoot and undershoot are 58 mV and 89 mV, respectively, the minimum recovery time is 1.2 μs. The worst-case phase margin is 64° over the full load range, the power supply rejection ratio is 99.2 dB@10 kHz in the unloaded state. The worst-case rate of load regulation rate and line regulation under different process corners are 0.016 mV/mA and 5.1 mV/V, respectively.

     

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