韩知宜,李博文,杨孟韬,等.一种面积与随机性均衡的DEM设计[J]. 微电子学与计算机,2024,41(5):117-126. doi: 10.19304/J.ISSN1000-7180.2023.0267
引用本文: 韩知宜,李博文,杨孟韬,等.一种面积与随机性均衡的DEM设计[J]. 微电子学与计算机,2024,41(5):117-126. doi: 10.19304/J.ISSN1000-7180.2023.0267
HAN Z Y,LI B W,YANG M T,et al. A DEM design with balanced area and randomness[J]. Microelectronics & Computer,2024,41(5):117-126. doi: 10.19304/J.ISSN1000-7180.2023.0267
Citation: HAN Z Y,LI B W,YANG M T,et al. A DEM design with balanced area and randomness[J]. Microelectronics & Computer,2024,41(5):117-126. doi: 10.19304/J.ISSN1000-7180.2023.0267

一种面积与随机性均衡的DEM设计

A DEM design with balanced area and randomness

  • 摘要: 针对高速电流舵数模转换器(Digital-to-Analog Conversion, DAC)中电流源阵列不匹配问题,提出了一种基于随机结合的分组译码动态元素匹配(Dynamic-Element Matching, DEM)结构以提升DAC的转换性能。所提结构是一种基于随机旋转(Random Rotation-based Binary-weighted Selection, RRBS)的改进结构。该结构首先将输入数据分成高位数据与低位数据,接着将低位数据经过RRBS结构处理所得的结果逐位与高位数据结合进行第二次处理并得到最终输出。该结构在输入数据为3位与输入数据大于3位这两种情况下存在差异。使用MATLAB对提出结构的无杂散动态范围(Spurious Free Dynamic Range, SFDR)进行了仿真。首先给出该结构在不同分段方式与不同误差情况下的SFDR对比图,接着将不同DEM结构在不同误差下进行对比,最后对该结构在不同输入频率与误差的情况进行仿真对比。同时,给出了该结构在tsmc65工艺下的综合结果。在相同的系统周期下,该结构所占用的面积相比于RRBS结构的更小。通过仿真与综合结果可以看出,提出的DEM结构电路减小了电路面积;相比于未使用DEM的14位DAC,本结构可以使SFDR提高15 dB以上。

     

    Abstract: Aiming at the problem of current source array mismatch in high speed Digital-to-Analog Conversion (DAC), a Dynamic Element Matching (DEM) structure based on random combination is proposed to improve the conversion performance of DAC. The structure first divides the input data into high data and low data, and then the result of low data processed by Random Rotation-based Binary-weighted Selection (RRBS) structure is combined with high data for the second processing bit by bit and the final output is obtained. The structure is different when the input data is 3 bits and when the input data is larger than 3 bits. The Spurious Free Dynamic Range (SFDR) of the proposed structure is simulated by Matlab. Firstly, the SFDR comparison diagram of the structure under different segmentation methods and different errors is given. Then, different DEM structures are compared under different errors. Finally, the simulation comparison of the structure under different input frequencies and errors is carried out. The circuit synthesis results of the proposed structure under tsmc65 process are given. Under the same system cycle, the area occupied by the structure is smaller than that of the RRBS structure. Through simulation and synthesis, it can be seen that the proposed DEM structure circuit reduces the circuit area. Compared with 14 bits DAC without DEM, the structure can increase SFDR by more than 15 dB.

     

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