Abstract: By analyzing the topology of KY converter and the reverse current problem, a NMOS drain-voltage sampling control loop is proposed. Reasonable sequential circuit and feedback controller are designed and more accurate zero-crossing turn-off is achieved. A fully integrated 100 MHz KY converter is designed based on a standard 0.18 μm CMOS process. The simulation results show that the reverse current is reduced. The peak efficiency is 81.3% when input voltage is 1.8 V, output voltage is 2.5 V and load current is 150 mA. Improvement of 4.5% is achieved compared with other circuit which turns off the switches based on the normal zero-crossing signal of inductor current.