Abstract: A solution of cache error detection and correction based on LEON2 processor was brought forward in this paper, to meet the fault tolerance requirements of radiation hardened microprocessor, especially for Multi-Bit Upset caused by single event effect in cache. Rather, parallel BCH (Bose-Chaudhuri-Hocquenghem) encoder and decoder were designed for tag memory and data memory of instruction cache and data cache, which could achieve error detection up to four bits. Also it could handle the faults effectively after checking out them. Experimental results based on LEON2 showed that this design could efficiently handle multi-bit error due to single event effect in cache, and its resource and performance overhead was acceptable, thus it would support for fault tolerance design of the future nanoscale microprocessor.