孙巧稚, 施慧彬. 基于FPGA的六级流水线MIPS处理器设计[J]. 微电子学与计算机, 2015, 32(4): 31-34,39.
引用本文: 孙巧稚, 施慧彬. 基于FPGA的六级流水线MIPS处理器设计[J]. 微电子学与计算机, 2015, 32(4): 31-34,39.
shu
SUN Qiao-zhi, SHI Hui-bin. Design of a Six-stage Pipelined MIPS Processor Based on FPGA[J]. Microelectronics & Computer, 2015, 32(4): 31-34,39.
Citation: SUN Qiao-zhi, SHI Hui-bin. Design of a Six-stage Pipelined MIPS Processor Based on FPGA[J]. Microelectronics & Computer, 2015, 32(4): 31-34,39.
shu

基于FPGA的六级流水线MIPS处理器设计

Design of a Six-stage Pipelined MIPS Processor Based on FPGA

    摘要
  • 摘要: 设计出了一种兼容MIPS指令集的32位六级流水线嵌入式处理器.六级流水线的划分平衡了各个阶段的任务.并详细介绍了数据冲突和控制冲突的解决方法.该处理器使用FPGA实现,在DE2芯片上的运行时钟频率可达81.7 MHz.最后给出了设计的综合结果,并对该设计进行了软件仿真和硬件验证.

     

    Abstract: A 32-bit embedded six-stage pipelined processor is designed in this paper, which is compatible with MIPS instruction set. The six stages make the task of each stage balanced. The solutions to data hazards and control hazards in detail are given out. The processor is implemented in FPGA, and its clock frequency can be up to 81.7 MHz in DE2 development board. The comprehensive results of the design are presented, and the software simulation and hardware verification results prove the correctness of the design.

     

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